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| LMX2330L/LMX2331L/LMX2332L PLLatinum Low Power Dual Frequency Synthesizer for RF Personal Communications June 1999 LMX2330L/LMX2331L/LMX2332L PLLatinumTM Low Power Dual Frequency Synthesizer for RF Personal Communications LMX2330L LMX2331L LMX2332L 2.5 GHz/510 MHz 2.0 GHz/510 MHz 1.2 GHz/510 MHz Features n Ultra low current consumption n 2.7V to 5.5V operation n Selectable synchronous or asynchronous powerdown mode: ICC = 1 A typical at 3V n Dual modulus prescaler: LMX2330L (RF) 32/33 or 64/65 LMX2331L/32L (RF) 64/65 or 128/129 LMX2330L/31L/32L (IF) 8/9 or 16/17 n Selectable charge pump TRI-STATE (R) mode n Selectable charge pump current levels n Selectable FastlockTM mode n Upgrade and compatible to LMX233XA family General Description The LMX233XL family of monolithic, integrated dual frequency synthesizers, including prescalers, is to be used as a local oscillator for RF and first IF of a dual conversion transceiver. It is fabricated using National's 0.5 ABiC V silicon BiCMOS process. The LMX233XL contains dual modulus prescalers. A 64/65 or a 128/129 prescaler (32/33 or 64/65 in the 2.5 GHz LMX2330L) can be selected for the RF synthesizer and a 8/9 or a 16/17 prescaler can be selected for the IF synthesizer. LMX233XL, which employs a digital phase locked loop technique, combined with a high quality reference oscillator, provides the tuning voltages for voltage controlled oscillators to generate very stable, low noise signals for RF and IF local oscillators. Serial data is transferred into the LMX233XL via a three wire interface (Data, Enable, Clock). Supply voltage can range from 2.7V to 5.5V. The LMX233XL family features very low current consumption; LMX2330L -- 5.0 mA at 3V, LMX2331L -- 4.0 mA at 3V, LMX2332L -- 3.0 mA at 3V. The LMX233XL are available in a TSSOP 20-pin and CSP 24-pin surface mount plastic package. Applications n Portable Wireless Communications (PCS/PCN, cordless) n Cordless and cellular telephone systems n Wireless Local Area Networks (WLANs) n Cable TV tuners (CATV) n Other wireless communication systems Functional Block Diagram DS012806-1 TRI-STATE (R) is a registered trademark of National Semiconductor Corporation. FastlockTM, MICROWIRETM and PLLatinumTM are trademarks of National Semiconductor Corporation. (c) 1999 National Semiconductor Corporation DS012806 www.national.com Connection Diagrams Chip Scale Package (SLB) (Top View) Thin Shrink Small Outline Package (TM) (Top View) DS012806-2 Order Number LMX2330LTM, LMX2331LTM or LMX2332LTM NS Package Number MTC20 DS012806-39 Order Number LMX2330LSLB, LMX2331LSLB or LMX2332LSLB NS Package Number SLB24A Pin Descriptions Pin No. LMX233XLSLB 24-pinCSP Package 24 Pin No. LMX233XLTM 20-pin TSSOP Package 1 Pin Name VCC1 I/O Description -- Power supply voltage input for RF analog and RF digital circuits. Input may range from 2.7V to 5.5V. VCC1 must equal VCC2. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. Power Supply for RF charge pump. Must be VCC. Internal charge pump output. For connection to a loop filter for driving the input of an external VCO. Ground for RF digital circuitry. RF prescaler input. Small signal input from the VCO. RF prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Capacitor is optional with some loss of sensitivity. Ground for RF analog circuitry. Oscillator input. The input has a VCC/2 input threshold and can be driven from an external CMOS or TTL logic gate. Ground for IF digital, MICROWIRETM, FoLD, and oscillator circuits. Multiplexed output of the RF/IF programmable or reference dividers, RF/IF lock detect signals and Fastlock mode. CMOS output (see Programmable Modes). High impedance CMOS Clock input. Data for the various counters is clocked in on the rising edge, into the 22-bit shift register. Binary serial data input. Data entered MSB first. The last two bits are the control bits. High impedance CMOS input. 2 3 4 5 6 2 3 4 5 6 VP1 Do RF GND fIN RF fIN RF -- O -- I I 7 8 10 11 7 8 9 10 GND OSCin GND FoLD -- I -- O 12 14 11 12 Clock Data I I www.national.com 2 Pin Descriptions Pin No. LMX233XLSLB 24-pinCSP Package 15 (Continued) Pin No. LMX233XLTM 20-pin TSSOP Package 13 Pin Name LE I/O Description I Load enable high impedance CMOS input. When LE goes HIGH, data stored in the shift registers is loaded into one of the 4 appropriate latches (control bit dependent). Ground for IF analog circuitry. IF prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Capacitor is optional with some loss of sensitivity. IF prescaler input. Small signal input from the VCO. Ground for IF digital, MICROWIRE, FoLD, and oscillator circuits. IF charge pump output. For connection to a loop filter for driving the input of an external VCO. Power Supply for IF charge pump. Must be VCC. Power supply voltage input for IF analog, IF digital, MICROWIRE, FoLD, and oscillator circuits. Input may range from 2.7V to 5.5V. VCC2 must equal VCC1. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. No connect. 16 17 14 15 GND fIN IF -- I 18 19 20 22 23 16 17 18 19 20 fIN IF GND Do IF VP2 VCC2 I -- O -- -- 1, 9, 13, 21 X NC -- 3 www.national.com Block Diagram DS012806-3 Note: The RF prescaler for the LMX2331L/32L is either 64/65 or 128/129, while the prescaler for the LMX2330L is 32/33 or 64/65. Note: VCC1 supplies power to the RF prescaler, N-counter, R-counter and phase detector. VCC2 supplies power to the IF prescaler, N-counter, phase detector, R-counter along with the OSCin buffer, MICROWIRE, and FoLD. VCC1 and VCC2 are clamped to each other by diodes and must be run at the same voltage level. Note: VP1 and VP2 can be run separately as long as VP VCC. www.national.com 4 Absolute Maximum Ratings 2) (Notes 1, Recommended Operating Conditions Power Supply Voltage VCC VP Operating Temperature (TA) 2.7V to 5.5V VCC to +5.5V -40C to +85C If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Power Supply Voltage VCC VP Voltage on Any Pin with GND = 0V (VI) Storage Temperature Range (TS) Lead Temperature (solder 4 sec.) (TL) -0.3V to +6.5V -0.3V to +6.5V -0.3V to VCC+0.3V -65C to +150C +260C Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Note 2: This device is a high performance RF integrated circuit with an ESD rating <2 keV and is ESD sensitive. Handling and assembly of this device should only be done at ESD protected work stations. Electrical Characteristics VCC = 3.0V, VP = 3.0V; -40C < TA < 85C, except as specified Symbol ICC Power Supply Current Parameter LMX2330L RF + IF LMX2330L RF Only LMX2331L RF + IF LMX2331L RF Only LMX2332L IF + RF LMX2332L RF Only LMX233xL IF Only ICC-PWDN Powerdown Current fIN RF Operating Frequency fIN IF fOSC f PfIN RF PfIN IF VOSC VIH VIL IIH IIL IIH IIL VOH VOL tCS tCH tCWH tCWL Operating Frequency Oscillator Frequency Maximum Phase Detector Frequency RF Input Sensitivity IF Input Sensitivity Oscillator Sensitivity High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current Oscillator Input Current Oscillator Input Current High-Level Output Voltage (for FoLD, pin number 10) Low-Level Output Voltage (for FoLD, pin number 10) Data to Clock Set Up Time Data to Clock Hold Time Clock Pulse Width High Clock Pulse Width Low 5 Conditions VCC = 2.7V to 5.5V Value Min Typ 5.0 4.0 4.0 3.0 3.0 2.0 1.0 Max 6.6 5.2 5.4 4.0 4.1 2.7 1.4 10 2.5 2.0 1.2 510 40 Units mA (Note 3) LMX2330L LMX2331L LMX2332L LMX233xL 0.5 0.2 0.1 45 5 10 VCC = 3.0V VCC = 5.0V VCC = 2.7V to 5.5V OSCin (Note 4) (Note 4) VIH = VCC = 5.5V (Note 4) VIL = 0V, VCC = 5.5V (Note 4) VIH = VCC = 5.5V VIL = 0V, VCC = 5.5V IOH = -500 A IOL = 500 A See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing 50 10 50 50 -15 -10 -10 0.5 0.8 VCC 1 A GHz MHz MHz MHz 0 0 0 dBm dBm dBm VPP V 0.2 VCC -1.0 -1.0 1.0 1.0 100 -100 VCC - 0.4 0.4 V A A A A V V ns ns ns ns www.national.com Electrical Characteristics Symbol tES tEW Parameter (Continued) VCC = 3.0V, VP = 3.0V; -40C < TA < 85C, except as specified Conditions See Data Input Timing See Data Input Timing Value Min 50 50 Typ Max Units ns ns Clock to Load Enable Set Up Time Load Enable Pulse Width Note 3: Clock, Data and LE = GND or Vcc. Note 4: Clock, Data and LE does not include fIN RF, fIN IF and OSCIN. Charge Pump Characteristics VCC = 3.0V, VP = 3.0V; -40C < TA 85C, except as specified Symbol IDo-SOURCE IDo-SINK IDo-SOURCE IDo-SINK IDo-TRI IDo-SINK vs IDo-SOURCE IDo vs VDo IDo vs TA Charge Pump TRI-STATE Current CP Sink vs Source Mismatch (Note 7) CP Current vs Voltage (Note 6) CP Current vs Temperature (Note 8) Parameter Charge Pump Output Current Conditions VDo = VP/2, ICPo VDo = VP/2, ICPo VDo = VP/2, ICPo VDo = VP/2, ICPo = HIGH (Note 5) = HIGH (Note 5) = LOW (Note 5) = LOW (Note 5) -2.5 3 10 10 Value Min Typ -4.0 4.0 -1 1 2.5 10 15 Max Units mA mA mA mA nA % % % 0.5V VDo VP - 0.5V -40C < TA < 85C VDo = VP/2 TA = 25C 0.5 VDo VP - 0.5V TA = 25C VDo = VP/2 -40C TA 85C Note 5: See PROGRAMMABLE MODES for ICPo description. www.national.com 6 Charge Pump Current Specification Definitions DS012806-37 I1 = CP sink current at VDo = VP - V I2 = CP sink current at VDo = VP/2 I3 = CP sink current at VDo = V I4 = CP source current at VDo = VP - V I5 = CP source current at VDo = VP/2 I6 = CP source current at VDo = V V = Voltage offset from positive and negative rails. Dependent on VCO tuning range relative to VCC and ground. Typical values are between 0.5V and 1.0V. Note 6: IDo vs VDo = Charge Pump Output Current magnitude variation vs Voltage = and [12 * {|I4| - |I6|}]/[12 * {|I4| + |I6|}] * 100% Charge Pump Output Current Sink vs Source Mismatch = [12 * {|I1| - |I3|}]/[12 * {|I1| + |I3|}] * 100% Note 7: IDo-sink vs IDo-source = Note 8: IDo vs TA = [|I2| - |I5|]/[12 * {|I2| + |I5|}] * 100% Charge Pump Output Current magnitude variation vs Temperature = and [|I5 @ temp| - |I5 @ 25C|]/|I5 @ 25C| * 100% [|I2 @ temp| - |I2 @ 25C|]/|I2 @ 25C| * 100% 7 www.national.com RF Sensitivity Test Block Diagram DS012806-38 Note 1: N = 10,000 R = 50 P = 64 Note 2: Sensitivity limit is reached when the error of the divided RF output, FoLD, is 1 Hz. Typical Performance Characteristics ICC vs VCC LMX2330L ICC vs VCC LMX2331L DS012806-19 DS012806-20 ICC vs VCC LMX2332L IDo TRI-STATE vs Do Voltage DS012806-21 DS012806-22 www.national.com 8 Typical Performance Characteristics Charge Pump Current vs Do Voltage ICP = HIGH (Continued) Charge Pump Current vs Do Voltage ICP = LOW DS012806-23 DS012806-24 Charge Pump Current Variation (See (Note 6) under Charge Pump Current Specification Definitions) Sink vs Source Mismatch (See (Note 7) under Charge Pump Current Specification Definitions) DS012806-25 DS012806-26 9 www.national.com Typical Performance Characteristics RF Input Impedance VCC = 2.7V to 5.5V, fIN = 50 MHz to 3 GHz (Continued) IF Input Impedance VCC = 2.7V to 5.5V, fIN = 50 MHz to 1000 MHz DS012806-28 DS012806-27 LMX2330L RF Sensitivity vs Frequency LMX2331L RF Sensitivity vs Frequency DS012806-29 DS012806-30 www.national.com 10 Typical Performance Characteristics LMX2332L RF Sensitivity vs Frequency (Continued) IF Input Sensitivity vs Frequency DS012806-31 DS012806-32 Oscillator Input Sensitivity vs Frequency DS012806-33 11 www.national.com Functional Description The simplified block diagram below shows the 22-bit data register, two 15-bit R Counters and the 15- and 18-bit N Counters (intermediate latches are not shown). The data stream is clocked (on the rising edge of Clock) into the DATA register, MSB first. The data stored in the shift register is loaded into one of 4 appropriate latches on the rising edge of LE. The last two bits are the Control Bits. The DATA is transferred into the counters as follows: Control Bits C1 0 0 1 1 C2 0 1 0 1 IF R Counter RF R Counter IF N Counter RF N Counter DATA Location DS012806-6 PROGRAMMABLE REFERENCE DIVIDERS (IF AND RF R COUNTERS) If the Control Bits are 00 or 01 (00 for IF and 01 for RF) data is transferred from the 22-bit shift register into a latch which sets the 15-bit R Counter. Serial data format is shown below. DS012806-7 15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER) Divide Ratio 3 4 R 0 0 R 0 0 R 0 0 R 0 0 R 0 0 R 0 0 R 9 0 0 R 8 0 0 R 7 0 0 R 6 0 0 R 5 0 0 R 4 0 0 R 3 0 1 R 2 1 0 R 1 1 0 15 14 13 12 11 10 * 32767 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 Notes: Divide ratios less than 3 are prohibited. Divide ratio: 3 to 32767 R1 to R15: These bits select the divide ratio of the programmable reference divider. Data is shifted in MSB first. www.national.com 12 Functional Description (Continued) PROGRAMMABLE DIVIDER (N COUNTER) The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control Bits are 10 or 11 (10 for IF counter and 11 for RF counter) data is transferred from the 22-bit shift register into a 4-bit or 7-bit latch (which sets the Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter), MSB first. Serial data format is shown below. For the IF N counter bits 5, 6, and 7 are don't care bits. The RF N counter does not have don't care bits. DS012806-8 7-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER) RF Divide Ratio A 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 N 7 N 6 N 5 N 4 N 3 N 2 N 1 IF Divide Ratio A 0 1 X X X X X X 0 0 0 0 0 0 0 1 N 7 N 6 N 5 N 4 N 3 N 2 N 1 * 127 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 15 * X * X * X * 1 * 1 * 1 * 1 Notes: Divide ratio: 0 to 127 BA X = DON'T CARE condition 11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER) Divide Ratio B 3 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 N 18 N 17 N 16 N 15 N 14 N 13 N 12 N 11 N 10 N 9 N 8 * 2047 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 Note: Divide ratio: 3 to 2047 (Divide ratios less than 3 are prohibited) BA PULSE SWALLOW FUNCTION fVCO = [(P x B) + A] x fOSC/R fVCO: Output frequency of external voltage controlled oscillator (VCO) B: Preset divide ratio of binary 11-bit programmable counter (3 to 2047) A: fOSC: R: P: Preset divide ratio of binary 7-bit swallow counter (0 A 127 {RF}, 0 A 15 {IF}, A B) Output frequency of the external reference frequency oscillator Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767) Preset modulus of dual moduIus prescaler (for IF; P = 8 or 16; for RF; LMX2330L: P = 32 or 64 LMX2331L/32L: P = 64 or 128) 13 www.national.com Functional Description PROGRAMMABLE MODES (Continued) Several modes of operation can be programmed with bits R16-R20 including the phase detector polarity, charge pump TRI-STATE and the output of the FoLD pin. The prescaler and powerdown modes are selected with bits N19 and N20. The programmable modes are shown in Table 1. Truth table for the programmable modes and FoLD output are shown in Table 2 and Table 3. TABLE 1. Programmable Modes C1 0 0 C2 0 1 R16 IF Phase Detector Polarity RF Phase Detector Polarity C1 1 1 C2 0 1 N19 IF Prescaler RF Prescaler RF ICPo R17 IF ICPo R18 IF Do TRI-STATE RF Do TRI-STATE N20 Pwdn IF Pwdn RF RF LD RF Fo R19 IF LD R20 IF Fo TABLE 2. Mode Select Truth Table Phase Detector Polarity (Note 11) 0 1 Negative Positive Do TRI-STATE (Note 9) Normal Operation TRI-STATE ICPo (Note 10) LOW HIGH IF Prescaler 8/9 16/17 2330L RF Prescaler 32/33 64/65 2331L/32L RF Prescaler 64/65 128/129 Pwdn (Note 9) Pwrd Up Pwrd Dn Note 9: Refer to POWERDOWN OPERATION in Functional Description. Note 10: The ICPo LOW current state = 1/4 x ICPo HIGH current. Note 11: PHASE DETECTOR POLARITY Depending upon VCO characteristics, R16 bit should be set accordingly: (see figure right) When VCO characteristics are positive like (1), R16 should be set HIGH; When VCO characteristics are negative like (2), R16 should be set LOW. VCO Characteristics DS012806-9 www.national.com 14 Functional Description RF R[19] (RF LD) 0 0 1 1 X X X X 0 0 1 1 X = don't care condition (Continued) TABLE 3. The FoLD (Pin 10) Output Truth Table IF R[19] (IF LD) 0 1 0 1 0 0 1 1 0 1 0 1 RF R[20] (RF Fo) 0 0 0 0 0 1 0 1 1 1 1 1 IF R[20] (IF Fo) 0 0 0 0 1 0 1 0 1 1 1 1 Fo Output State Disabled (Note 12) IF Lock Detect (Note 13) RF Lock Detect (Note 13) RF/IF Lock Detect (Note 13) IF Reference Divider Output RF Reference Divider Output IF Programmable Divider Output RF Programmable Divider Output Fastlock (Note 14) IF Counter Reset (Note 15) RF Counter Reset (Note 15) IF and RF Counter Reset (Note 15) Note 12: When the FoLD output is disabled, it is actively pulled to a low logic state. Note 13: Lock detect output provided to indicate when the VCO frequency is in "lock." When the loop is locked and a lock detect mode is selected, the pins output is HIGH, with narrow pulses LOW. In the RF/IF lock detect mode a locked condition is indicated when RF and IF are both locked. Note 14: The Fastlock mode utilizes the FoLD output pin to switch a second loop filter damping resistor to ground during fastlock operation. Activation of Fastlock occurs whenever the RF loop's lcpo magnitude bit #17 is selected HIGH (while the #19 and #20 mode bits are set for Fastlock). Note 15: The IF Counter Reset mode resets IF PLL's R and N counters and brings IF charge pump output to a TRI-STATE condition. The RF Counter Reset mode resets RF PLL's R and N counters and brings RF charge pump output to a TRI-STATE condition. The IF and RF Counter Reset mode resets all counters and brings both charge pump outputs to a TRI-STATE condition. Upon removal of the Reset bits then N counter resumes counting in "close" alignment with the R counter. (The maximum error is one prescaler cycle.) POWERDOWN OPERATION Synchronous and asynchronous powerdown modes are both available by MICROWIRE selection. Synchronously powerdown occurs if the respective loop's R18 bit (Do TRI-STATE) is LOW when its N20 bit (Pwdn) becomes HI. Asynchronous powerdown occurs if the loop's R18 bit is HI when its N20 bit becomes HI. In the synchronous powerdown mode, the powerdown function is gated by the charge pump to prevent unwanted frequency jumps. Once the powerdown program bit N20 is loaded, the part will go into powerdown mode when the charge pump reaches a TRI-STATE condition. In the asynchronous powerdown mode, the device powers down immediately after the LE pin latches in a HI condition on the powerdown bit N20. Activation of either the IF or RF PLL powerdown conditions in either synchronous or asynchronous modes forces the respective loop's R and N dividers to their load state condition and debiasing of its respective fIN input to a high impedance state. The oscillator circuitry function does not become disabled until both IF and RF powerdown bits are activated. The MICROWIRE control register remains active and capable of loading and latching data during all of the powerdown modes. The device returns to an actively powered up condition in either synchronous or asynchronous modes immediately upon LE latching LOW data into bit N20. Powerdown Mode Select Table R18 0 1 0 1 N20 0 0 1 1 Powerdown Status PLL Active PLL Active (Charge Pump Output TRI-STATE) Synchronous Powerdown Initiated Asynchronous Powerdown Initiated 15 www.national.com Functional Description SERIAL DATA INPUT TIMING (Continued) DS012806-10 Note 1: Parenthesis data indicates programmable reference divider data. Data shifted into register on clock rising edge. Data is shifted in MSB first. Note 2: tcs = Data to Clock Set-Up Time tCH = Data to Clock Hold Time tCWH = Clock Pulse Width High tCWL = Clock Pulse Width Low tES = Clock to Load Enable Set-Up Time tEW = Load Enable Pulse Width Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an edge rate of 0.6 V/ns with amplitudes of 2.2V @ VCC = 2.7V and 2.6V @ VCC = 5.5V. PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS DS012806-11 Notes: Phase difference detection range: -2 to +2 The minimum width pump up and pump down current pulses occur at the Do pin when the loop is locked. R16 = HIGH www.national.com 16 Typical Application Example DS012806-12 Operational Notes: * VCO is assumed AC coupled. ** RIN increases impedance so that VCO output power is provided to the load rather than the PLL. Typical values are 10 to 200 depending on the VCO power level. fIN RF impedance ranges from 40 to 100. fIN IF impedances are higher. *** Adding RC filters to the VCC lines is recommended to reduce loop-to-loop noise coupling. DS012806-13 Application Hints: Proper use of grounds and bypass capacitors is essential to achieve a high level of performance. Crosstalk between pins can be reduced by careful board layout. This is an electrostatic sensitive device. It should be handled only at static free work stations. 17 www.national.com Application Information A block diagram of the basic phase locked loop is shown in Figure 1. DS012806-14 FIGURE 1. Basic Charge Pump Phase Locked Loop LOOP GAIN EQUATIONS A linear control system model of the phase feedback for a PLL in the locked state is shown in Figure 2. The open loop gain is the product of the phase comparator gain (K), the VCO gain (KVCO/s), and the loop filter gain Z(s) divided by the gain of the feedback counter modulus (N). The passive loop filter configuration used is displayed in Figure 3, while the complex impedance of the filter is given in Equation (1). DS012806-15 FIGURE 2. PLL Linear Model DS012806-16 FIGURE 3. Passive Loop Filter (1) The time constants which determine the pole and zero frequencies of the filter transfer function can be defined as (2) and (3) T2 = R2 * C2 The 3rd order PLL Open Loop Gain can be calculated in terms of frequency, , the filter time constants T1 and T2, and the design constants K, KVCO, and N. (4) From Equations (2), (3) we can see that the phase term will be dependent on the single pole and zero such that the phase margin is determined in Equation (5). (5) () = tan -1 ( * T2) - tan-1 ( * T1) + 180 A plot of the magnitude and phase of G(s)H(s) for a stable loop, is shown in Figure 4 with a solid trace. The parameter p shows the amount of phase margin that exists at the point the gain drops below zero (the cutoff frequency wp of the loop). In a critically damped system, the amount of phase margin would be approximately 45 degrees. If we were now to redefine the cut off frequency, wp', as double the frequency which gave us our original loop bandwidth, wp, the loop response time would be approximately halved. Because the filter attenuation at the comparison frequency also diminishes, the spurs would have increased by approximately 6 dB. In the proposed Fastlock scheme, the higher spur levels and wider loop filter conditions would exist only during the initial lock-on phase -- just long enough to reap the benefits of locking faster. The objective would be to open up the loop bandwidth but not introduce any additional complications or compromises related to our original design criteria. We would ideally like to momentarily shift the curve of Figure 4 over to a different cutoff frequency, illustrated by the dotted line, without affecting the relative open loop gain and phase relationships. To maintain the same gain/phase relationship at twice the original cutoff frequency, other terms in the gain and phase Equation (4) and Equation (5) will have to compensate by the corresponding "1/w" or "1/w2" factor. Examination of equations Equations (2), (3) and Equation (5) indicates the damping resistor variable R2 could be chosen to compensate the "w"' terms for the phase margin. This implies that another resistor of equal value to R2 will need to be switched in parallel with R2 during the initial lock period. We must also insure that the magnitude of the open loop gain, H(s)G(s) is equal to zero at wp' = 2wp. Kvco, K, N, or the net product of these terms can be changed by a factor of 4, to counteract the w2 term present in the denominator of Equation (2) and Equation (3). The K term was chosen to complete the transformation because it can readily be switched www.national.com 18 Application Information (Continued) between 1X and 4X values. This is accomplished by increasing the charge pump output current from 1 mA in the standard mode to 4 mA in Fastlock. DS012806-17 FIGURE 4. Open Loop Response Bode Plot FASTLOCK CIRCUIT IMPLEMENTATION A diagram of the Fastlock scheme as implemented in National Semiconductors LMX233XL PLL is shown in Figure 5. When a new frequency is loaded, and the RF Icpo bit is set high the charge pump circuit receives an input to deliver 4 times the normal current per unit phase error while an open drain NMOS on chip device switches in a second R2 resistor element to ground. The user calculates the loop filter component values for the normal steady state considerations. The device configuration ensures that as long as a second identical damping resistor is wired in appropriately, the loop will lock faster without any additional stability considerations to account for. Once locked on the correct frequency, the user can return the PLL to standard low noise operation by sending a MICROWIRE instruction with the RF Icpo bit set low. This transition does not affect the charge on the loop filter capacitors and is enacted synchronous with the charge pump output. This creates a nearly seamless change between Fastlock and standard mode. DS012806-18 FIGURE 5. Fastlock PLL Architecture 19 www.national.com Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead (0.173" Wide) Thin Shrink Small Outline Package (TM) Order Number LMX2330LTM, LMX2331LTM or LMX2332LTM *For Tape and Reel (2500 units per reel) Order Number LMX2330LTMX, LMX2331LTMX or LMX2332LTMX NS Package Number MTC20 www.national.com 20 LMX2330L/LMX2331L/LMX2332L PLLatinum Low Power Dual Frequency Synthesizer for RF Personal Communications Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Pin Chip Scale Package Order Number LMX2330LSLB, LMX2331LSLB or LMX2332LSLB *For Tape and Reel (2500 Units per Reel) Order Number LMX2330LSLBX, LMX2331LSLBX or LMX2332LSLBX NS Package Number SLB24A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Francais Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. |
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